The present invention relates to a nonvolatile, integrated-circuit memory array such as an electrically-erasable, electrically-programmable read-only-memory (EEPROM) array, and more particularly to an EEPROM array in which the memory cells are erased by Fowler-Nordheim tunnelling.
EEPROMs employing single transistor memory cells, using hot-carrier injection for programming and Fowler-Nordheim tunnelling for erasure have been described in: (a) "A Single Transistor EEPROM cell and its implementation in a 512K CMOS EEPROM", S. Mukherjee et al., IEDM 1985 (p. 616-619); and (b) "A 90ns 100K Erase/Program Cycle Megabit Flash Memory", V. Kynett et al., ISSCC 1989 (p. 140-141). Reference (a) is also discussed in U.S. Pat. No. 4,698,787.
During cell erasing, appropriate erasing voltages applied to the control-gates/wordlines and the source lines allow removal of a selected charge from the floating gate. Normally, all control gates are grounded during erase operation of a flash EEPROM or, in the alternative, all control gates have the same negative voltage applied.
The erase voltage threshold Vt window of a flash EEPROM is affected by the amount of source/drain diffusion that underlaps the floating gate on, for example, the source side. Field-oxide rounding results in different amounts of underlap depending on how much of the gate resides over the rounded edge of the field oxide. Because of misalignment, the amount of underlap differs between alternate rows of cells, where the cells are constructed in the manner described above-listed references. If the identical erasing pulses are used to erase all of the rows of cells, a bimodal, with possibly wide-margin, distribution of voltage thresholds Vt results. The bimodal distribution adversely affects the reading and programming operations of the nonvolatile memory.
Accordingly, a need exists for a circuit to correct, or narrow the margin of, the bimodal distribution of voltage threshold characteristics caused by different underlap in misaligned alternating rows of cells.